The present invention relates to a logic simulation system and more particularly to a stimulus engine for an event driven logic simulator.
Event driven logic simulators, whether implemented in software or hardware, represent logic activity as a series of "events." These events consist of a net address, a time parameter and a new logic state for the net. Every net (or node) has a driving device and a unique net address. The time parameter may be in absolute time or a time interval relative to a previous event. The logic state is typically made up of three or more values and three or more strengths. Typical values are logic zero, logic one and undefined. Typical strengths are driving, resistive, and high impedance.
Simulation of a logic network requires that events be presented to the external nets (the I/O pins) of the simulated logic network in order to stimulate logic activity within the network. As longer periods of time are simulated, a larger number of events is required to stimulate the external nets. The files which store these event streams tend to become extremely large, which results in three problems:
1. The memory and disk storage requirements can become excessive.
2. The time required to edit (insert and delete events) these files can become excessive.
3. The time required to present the files to the logic simulator can become excessive since disk access is required during the simulation if the file cannot be stored in local random access memory (RAM).
In addition, the creation of large stimulus files has traditionally been a difficult and time consuming task, since the languages for specification of the stimulus have been closely tied to the simulation algorithms rather than "high level" languages.